1. Field of the Invention
The present invention relates generally to a communication system which processes data on a frame unit basis, and in particular, to a channel encoding device and a method thereof.
2. Description of the Related Art
In communication systems for processing voice, character, image and video signals, data is generally transmitted on a frame unit basis. A frame is defined as a basic timing internal in the system. Further, in a system for communicating such frame data, a channel encoder for error correction should also encode data on the frame unit basis. In this case, the channel encoder performs zero tail biting to indicate the termination of each frame so that a decoder can efficiently decode the frames using that information. Encoder tail bits represent a fixed sequence of bits added to the end of a data frame to reset the convolutional encoder to a known state. An IS-95 system typically uses a non-recursive systematic convolutional encoder, which adds a sequence of zero (0) bits to the end of each frame equal to the number of delays, to implement frame termination. However, in contrast to the non-recursive systematic convolutional encoder, a recursive systematic encoder cannot add the zero bits to the end of the frame to implement the frame termination because input bits are fed back to the delays.
FIG. 1 illustrates a block diagram of a conventional parallel turbo encoder, which is disclosed in U.S. Pat. No. 5,446,747 issued to Berrou. The encoder of FIG. 1 is one type of conventional recursive systematic encoder. The turbo encoder encodes an N-bit input frame into parity symbols using two simple constituent encoders, and can be configured to have either a parallel or serial structure. In addition, the turbo encoder of FIG. 1 uses recursive systematic convolutional codes as constituent codes.
The turbo encoder of FIG. 1 includes an interleaver 120 interposed between a first constituent encoder 110 and a second constituent encoder 130. The interleaver 120 has the same size as a frame length, N, of input data bits and re-arranges the order of the data bits input to the second constituent encoder 130 to reduce the correlation between the outputs of the first and second encoders.
The first constituent encoder 110 encodes the input data bits and the interleaver 120 interleaves (or randomizes) the bits in the input data stream according to a specified rule so that burst errors introduced by the channel can be converted to random errors. The second constituent encoder 130 encodes the output of the interleaver 120.
FIG. 2 is a diagram illustrating a termination scheme in the recursive systematic convolutional encoder of FIG. 1. For more detailed information, see D. Divsalar and F. Pollara, xe2x80x9cOn the Design of Turbo Dodesxe2x80x9d, TDA Progress Report 42-123, Nov. 15, 1995. Here, frame data input to the first and second constituent encoders 110 and 130 is assumed to be 20-bit data. In FIG. 2, D1-D4 denotes delays and XOR1-XOR6 exclusive OR gates.
Referring to FIG. 2, the operative steps to perform encoding are as follows. A switch SW1 is maintained in the ON position and a switch SW2 is maintained in the OFF position. Then, the 20-bit input frame data is applied in sequence to the delays D1-D4 and exclusively ORed by the exclusive OR gates XOR1-XOR6, thus outputting encoded bits at the output of exclusive OR gate XOR6. When the 20 data bits are all encoded in this manner, the switch SW1 is switched OFF and the switch SW2 is switched ON, for frame termination. Then, the XOR gates XOR1-XOR4 exclusively OR the output data bits of the delays and the corresponding fed-back data bits, respectively, thereby outputting zero bits. The resulting zero bits are again input to the delays D1-D4 and stored therein. These zero bits input to the delays D1-D4 become tail bits, which are applied to a multiplexer.
The multiplexer multiplexes the encoded data bits and the tail bits output from the constituent encoder. The number of generated tail bits depends on the number of the delays included in the constituent encoders 110 and 130. The termination scheme of FIG. 2 generates 4 tail bits per frame plus additional encoded bits generated for each of the respective tail bits, undesirably increasing the overall final encoded bit count, which leads to a decrease in a bit rate. That is, when the bit rate is defined as;
Bit Rate=(the Number of Input Data Bits)/(the Number of Output Data Bits),
a constituent encoder having the structure of FIG. 2 has a bit rate of
xe2x80x83Bit Rate=(the Number of Input Data Bits)/{(the Number of Encoded Data Bits)+(the Number of Tail Bits)+(the Number of Encoded Bits for the Tail Bits)}.
Accordingly, in FIG. 2, since the frame data is composed of 20 bits and the number of delays equals 4, the bit rate becomes 20/28.
It is therefore apparent that the recursive, systematic convolutional encoder""s performance depends upon the tailing method, because it is difficult to perfectly tail the turbo codes.
It is, therefore, an object of the present invention to provide a device and method for performing channel encoding/decoding using a frame structure, in which predetermined bits are inserted, in a recursive systematic encoder for a communication system.
It is another object of the present invention to provide a recursive systematic channel encoding device and method for inserting bits having a specific value in frame data at predefined positions before channel encoding.
It is further another object of the present invention to provide a channel decoding device and method for decoding channel coded data transmitted from a channel encoder, wherein the bits having specific values were inserted at predetermined positions of frame data during channel encoding.
It is yet another object of the present invention to provide a device and method for inserting a bit having a specific value at a specific symbol position out of channel coded symbols, and performing soft-decision decoding using the bit having the specific value to increase channel decoding performance.
In accordance with one aspect of the present invention, there is provided a channel decoding device for a receiver which receives symbols coded by inserting at least one specific bit in a frame data at a predetermined position. The channel decoding device comprises a symbol inserter receiving the symbols, for inserting a symbol having a specific value at predetermined specific bit insert position and outputting the received symbols at other positions; and a decoder for decoding symbols output from the symbol inserter.
More specifically, the channel decoding device comprises a demultiplexer receiving the symbols, for demultiplexing the received symbols into a data symbol, a first parity symbol and a second parity symbol; a symbol inserter for inserting a symbol having a specific value at predetermined specific bit insert position of the data symbol and outputting the received symbols at other positions; a first decoder for performing soft decision for the data symbol output from the symbol inserter and the first parity symbol to generate a first decoded symbol; a first interleaver for interleaving an output of the first decoder; a second decoder for performing soft decision for the first decoded symbol output from the first interleaver and the second parity symbol to generate a second decoded symbol; a hard-decision element for performing hard decision for the second decoded data; and a first deinterleaver for deinterleaving an output of the hard-decision element.
In accordance with another aspect of the present invention, there is provided a channel decoding method for a receiver which receives symbols coded by inserting at least one specific bit in a frame data at a predetermine position. The channel decoding method comprises the steps of: receiving the symbols, inserting a symbol having a specific value at a predetermined specific bit insert position and outputting the received symbols at other positions; and decoding the received symbols using the inserted symbol having the specific value.
More specifically, the channel decoding method comprises the steps of a) receiving the symbols, and demultiplexing the received symbols into a data symbol, a first parity symbol and a second parity symbol; b) inserting a symbol having a specific value at a predetermined specific bit insert position of the data symbol and outputting the received symbols at other positions; c) performing soft decision for the data symbol, in which the symbol having the specific value is inserted, and the first parity symbol to generate a first decoded symbol; d) interleaving the first decoded symbol; e) performing soft decision for the interleaved first decoded symbol and the second parity symbol to generate a second decoded symbol; f) deinterleaving the second decoded symbol; g) initializing a corresponding symbol of the deinterleaved second symbol to the specific value at an insert position, and returning to step c) to repeat the steps c) to e); h) upon completion of the steps c) to e), performing hard decision for the second decoded data; and i) deinterleaving the hard-decision processed second decoded symbol.